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fn8131 rev 3.00 page 1 of 19 december 9, 2015 fn8131 rev 3.00 december 9, 2015 X5323, x5325 (repla ces x25323, x25325) cpu supervisor with 32kbit spi eeprom datasheet these devices combine four popular functions, power-on reset control, watchdog timer , supply voltage supervision, and block lock protect serial eeprom memory in one package. this combination lo wers system cost, reduces board space requirements, and increases reliability. applying power to t he device activates the power-on reset circuit which holds reset /reset active fo r a period of time. this allows the power supp ly and oscillator to stabilize before the processo r can execute code. the watchdog timer provides an independent protection mechanism for microcontroller s. when the microcontroller fails to restart a timer within a selectable time out interval, the device activates the reset /reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the devices low v cc detection circuitry protects the users system from low voltage condit ions, resetting the system when v cc falls below the minimum v cc trip point. reset /reset is asserted until v cc returns to proper operating level and stabilizes. five industry standard v trip thresholds are available, however, intersils unique circuits allow the threshold to be re programmed to meet custom requirements or to fi ne-tune the threshold for applications requiring higher precision. features ? selectable watchdog timer ?low v cc detection and reset assertion - five standard reset threshold voltages - re-program low v cc reset threshold voltage using special progra mming sequence - reset signal valid to v cc = 1v ? determine watchdog or low vo ltage reset with a volatile flag bit ? long battery life with low power consumption - <50a max standby c urrent, watchdog on - <1a max standby current, watchdog off - <400a max active current during read ? 32kbits of eeprom ? built-in inadverten t write protection - power-up/power-down protection circuitry - protect 0, 1/4, 1/ 2 or all of eeprom array with block lock ? protection - in circuit programmable rom mode ? 2mhz spi interface modes (0,0 and 1,1) ? minimize eeprom programming time - 32-byte page write mode - self-timed write cycle - 5ms write cycle time (typical) ? 2.7v to 5.5v and 4.5v to 5.5v power supply operation ? available packages - 14 ld tssop, 8 ld soic, 8 ld pdip ? pb-free (rohs compliant) block diagram watchdog timer reset data register command decode and control logic si so sck cs /wdi v cc reset and watchdog timebase power-on and generation v trip + - reset /reset reset low voltage status register protect logic 8kbits 8kbits 16kbits eeprom array watchdog transition detector wp X5323 = reset x5325 = reset v cc threshold reset logic
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 2 of 19 december 9, 2015 ordering information part number part marking v cc range (v) v trip range (v) temp range (c) package reset (active low) X5323pz-4.5a (note) (no longer available, recommended replacement: X5323s8z-4.5a) X5323p zal 4.5 to 5.5 4.5 to 4.75 0 to +70 8 ld pdip** (pb-free) X5323piz-4.5a (note) (no longer available, recommended replacement: X5323s8iz-4.5a) X5323p zam -40 to +85 8 ld pdip** (pb-free) X5323s8z-4.5a (note) X5323 zal 0 to +70 8 ld soic (pb-free) X5323s8iz-4.5a* (note) X5323 zam -40 to +85 8 ld soic (pb-free) X5323v14-4.5a X5323 val 0 to +70 14 ld tssop X5323pz (note) (no longer available, recommended replacement: X5323s8z) X5323p z 4.5 to 5.5 4.25 to 4.5 0 to +70 8 ld pdip** (pb-free) X5323piz (note) (no longer available, recommended replacement: X5323s8iz) X5323p zi -40 to +85 8 ld pdip** (pb-free) X5323s8z* (note) X5323 z 0 to +70 8 ld soic (pb-free) X5323s8iz* (note) X5323 zi -40 to +85 8 ld soic (pb-free) X5323pz-2.7a (note) (no longer available, recommended replacement: X5323s8z-2.7a) X5323p zan 2.7 to 5.5 2.85 to 3.0 0 to +70 8 ld pdip** (pb-free) X5323piz-2.7a (note) (no longer available, recommended replacement: X5323s8iz-2.7a) X5323p zap -40 to +85 8 ld pdip** (pb-free) X5323s8z-2.7a* (note) X5323 zan 0 to +70 8 ld soic (pb-free) X5323s8iz-2.7a* (note) X5323 zap -40 to +85 8 ld soic (pb-free) X5323pz-2.7 (note) (no longer available, recommended replacement: X5323s8z-2.7) X5323p zf 2.7 to 5.5 2.55 to 2.7 0 to +70 8 ld pdip** (pb-free) X5323piz-2.7 (note) (no longer available, recommended replacement: X5323s8iz-2.7) X5323p zg -40 to +85 8 ld pdip** (pb-free) X5323s8z-2.7* (note) X5323 zf 0 to +70 8 ld soic (pb-free) X5323s8iz-2.7* (note) X5323 zg -40 to +85 8 ld soic (pb-free) reset (active high) x5325s8z-4.5a (note) x5325 zal 4.5 to 5.5 4.5 to 4.75 0 to +70 8 ld soic (pb-free) x5325s8iz-4.5a (note) x5325 zam -40 to +85 8 ld soic (pb-free) x5325s8z* (note) x5325 z 4.5 to 5.5 4.25 to 4.5 0 to +70 8 ld soic (pb-free) x5325s8iz* (note) x5325 zi -40 to +85 8 ld soic (pb-free) x5325s8z-2.7a (note) x5325 zan 2.7 to 5.5 2.85 to 3.0 0 to +70 8 ld soic (pb-free) x5325s8iz-2.7a (note) x5325 zap -40 to +85 8 ld soic (pb-free) x5325s8z-2.7* (note) x5325 zf 2.7 to 5.5 2.55 to 2.7 0 to +70 8 ld s oic (pb-free) x5325s8iz-2.7* (note) x5325 zg -40 to +85 8 ld soic (pb-free) *add -t1 for tape and reel. please refer to tb347 for details on reel specifications. **pb-free pdips can be used for through hole wave solder proces sing only. they are not intended for use in reflow solder proce ssing applications. note: these intersil pb-free pl astic packaged products employ sp ecial pb-free material sets; molding compounds/die attach mater ials and 100% matte tin plate plus anneal - e3 termination finish, which is r ohs compliant and compatible with both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020.
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 3 of 19 december 9, 2015 pinouts X5323, x5325 (8 ld soic, pdip) top view X5323, x5325 (14 ld tssop) top view cs /wdi wp so 1 2 3 4 reset /reset 8 7 6 5 v cc v ss sck si so wp v ss 1 2 3 4 5 6 7 sck si 14 13 12 11 10 9 8 nc v cc nc cs /wdi nc nc nc nc reset /reset pin descriptions pin number (soic/pdip) pin number tssop pin name pin function 11cs /wdi chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvolatile wr ite cycle is underway, the device will be in the stand-by power mode. cs low enables the device, placing it in the active power mode. p rior to the start of any operation after power-up, a high to low transition on cs is required. watchdog input. a high to low transition on the wdi pin restarts the watchdog timer. the absence of a high to low transition within the watchdog time ou t period results in reset /reset going active. 22so serial output. so is a push/pull se rial data outpu t pin. a read cycle shifts data out on this pin. the falling edge of t he serial clock (sck ) clocks th e data out. 58si serial input. si is a serial data input pin. input all opcodes, byte address es, and memory data on this pin. the rising edge of the serial clock (sck) latches the inpu t data. send all opcodes (table 1), addresses and data msb first. 69sck serial clock. the serial clock controls the serial bus timing for data input and output. the rising edge of sck latches in the opcode, address, or data bits present on the si pin. the falling edge of sck changes the data output on the so pin. 36wp write protect. the wp pin works in conjunction with a nonvolatile wpen bit to lock the setting of the watchdog timer control and the memory write protect bits . 47v ss ground 814v cc supply voltage 7 13 reset / reset reset output . reset /reset is an active low/high, open drain output which goes acti ve whenever v cc falls below the minimum v cc sense level. it will remain active until v cc rises above the minimum v cc sense level for 200ms. reset /reset goes active if the watchdog timer is enabled and cs remains either high or low l onger than the selectable watchdog time out period. a falling edge of cs will reset the watchdog timer. reset /reset goes active on power- up at about 1v and remains active for 200ms after the power sup ply stabilizes. 3 to 5,10 to 12 nc no internal connections
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 4 of 19 december 9, 2015 principles of operation power-on reset application of power to the X5323/x5325 activates a power-on reset circuit. t his circuit goes active at about 1v and pulls t he reset /reset pin active. this signal prevents the system microprocessor from starting to operate with insufficient volta ge or prior to stabilization of the oscillator. as long as reset /reset pin is active, the dev ice will not respond to any read/write instruction. when v cc exceeds the device v trip value for 200ms (nominal) the circuit releases reset /reset, allowing the processor to begin executing code. low voltage monitoring during operation, the X5323/x5325 monitors the v cc level and asserts reset /reset if supply voltage falls below a preset minimum v trip . the reset /reset signal prevents the microprocessor from operating in a power fail or brown-out condition. the reset /reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. watchdog timer the watchdog timer circuit monitors the microprocessor activity by monitoring the wdi input. the microprocessor must toggle the cs /wdi pin per iodically to prevent a reset /reset signal. the cs /wdi pin must be toggled fr om high to low prior to the expiration of the watchdog time out period. the state of tw o nonvolatile control bits in the status register determine the watchdog timer period. the mic roprocessor can change these watchdog bits, or they may be locked by tying the wp pin low and setting the wpen bit high. v cc threshold reset procedure the X5323/x5325 ha s a standard v cc threshold (v trip ) voltage. this value will not chang e over normal operating and storage conditions. however , in applications where the standard v trip is not exactly right, or for higher precision in the v trip value, the X5323/x5325 thre shold may be adjusted. setting the v trip voltage this procedure sets the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure directly makes th e change. if the new setting is lower than the current setting , then it is nece ssary to reset t he trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold to the vcc pin and tie the cs /wdi pin and the wp pin high. reset /reset and so pins are left unconnected. then apply the progr amming voltage v p to both sck and si and pulse cs /wdi low then high. remove v p and the sequence is complete. resetting the v trip voltage this procedure sets the v trip to a native voltage level. for example, if the current v trip is 4.4v and the v trip is reset, the new v trip is something less than 1.7 v. this procedure must be used to set the voltage to a lower value. to reset the v trip voltage, apply a vol tage between 2.7v and 5.5v to the vcc pin. tie the cs /wdi pin, the wp pin, and the sck pin high. reset /reset and so pins are left unconnected. then apply th e programming voltage v p to the si pin only and pulse cs /wdi low then high. remove v p and the sequence is complete. sck si v p v p cs figure 1. set v trip voltage sck si v cc v p cs figure 2. reset v trip voltage
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 5 of 19 december 9, 2015 v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip - desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied = old v cc applied + error (v cc = v cc - 10mv) execute sequence reset v trip new v cc applied = old v cc applied - error error ? emax error < emax yes no error ?? emax emax = maximum desired error figure 3. v trip programming sequence flow chart X5323, 1 2 3 4 8 7 6 5 v trip adj. program nc nc v p reset v trip test v trip set v trip nc reset 4.7k ? 4.7k ? 10k ? 10k ? + figure 4. sample v trip reset circuit x5325
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 6 of 19 december 9, 2015 spi serial memory the memory portion of the devic e is a cmos serial eeprom array with intersils block lock protection. the array is inter nally organized as x8. the device f eatures a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes intersils proprietary direct write ? cell, providing a minimu m endurance of 100, 000 cycles and a minimum data retention of 100 years. the device is desi gned to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. it cont ains an 8-bit in struction regi ster that is accessed via the si input, with data being clocked in o n the rising edge of sck. cs must be low dur ing the entire operation. all instructions (t able 1), addresses and data are transferred msb first. data input on the si l ine is latched on the first ri sing edge of sck after cs goes low. data is output on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it again to resume operations where left off. write enable latch the device contains a write enabl e latch. this latch must be set before a write operation is i nitiated. the wren instruction will set the latch and the wrdi i nstruction will reset the latc h (figure 3). this latch is autom atically reset upon a power-up condition and after the completion of a valid w rite cycle. status register the rdsr instruction provides a ccess to the status register. the status register may be read at any time, even during a writ e cycle. the status register is formatted as follows: the write-in-progress (wip) bit is a volatile, read only bit an d indicates whether the device is busy with an internal nonvolatile write operation. t he wip bit is read using the rdsr instruction. when set to a 1, a nonvolatile write operation is in progress. when set to a 0, no write is in progress. the write enable latch (wel) bit indicates the status of the write enable latch. when wel = 1, the latch is set high and when wel = 0 the la tch is reset low. the wel bit is a volatile, read only bit. it can be set by the wren instruction and can be reset by the wrds instruction. the block lock bits, bl0 and b l1, set the leve l of block lock protection. these nonvolatile bits are progra mmed using the wrsr instruction and allow the us er to protect one quarter, one half, all or none of the eeprom array. any portion of the array that is block lock pr otected can be read b ut not written. it wi ll remain protected until the bl bit s are altered to disable block lock protection of that portion of memory. note: *instructions are shown m sb in leftmost position. instruct ions are transferred msb first. 7 65 43210 wpen flb wd1 wd0 bl1 bl0 wel wip table 1. instruction set instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operation s) sflb 0000 0000 set flag bit wrdi/rflb 0000 0100 reset the write enable latch/reset flag bit rsdr 0000 0101 read status register wrsr 0000 0001 write status register (watchdog, block lock, wpen and flag bits) read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address table 2. block protect matrix wren cmd status register device pin block block status register wel wpen wp protected block unprotected block wpen, bl0, bl1 wd0, wd1 0 x x protected protected protected 1 1 0 protected writable protected 1 0 x protected writable writable 1 x 1 protected writable writable
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 7 of 19 december 9, 2015 . the watchdog timer bits, wd0 and wd1, select the watchdog time out period. these nonvola tile bits are programmed with the wrsr instruction. the flag bit shows the status of a volatile latch that can be set and reset by the system using the sf lb and rflb instructions. the flag bit is aut omatically reset upon power-up . this flag can be used by the system to determine whether a reset occurs as a re sult of a watchdog time out or power failure. note: the watch dog timer is shipped disabled. (wd1 = 1, wd0 = 1. the factory def ault for memory block protection is none. (bl1 = 0, bl0 = 0). the nonvolatile wpen bit is p rogrammed using the wrsr instruction. this bit works in conjunction with the wp pin to provide an in-circuit programma ble rom function (table 2). wp is low and wpen bit programmed high disables all status register write operations. in circuit programmable rom mode this mechanism protects the bl ock lock and watchdog bits from inadvertent corruption. in the locked state (programmable rom mode) the wp pin is low and the nonvolatile bit wpen is 1. this mode disables nonvolatile writes to the devices status register. setting the wp pin low while wpen is a 1 while an internal write cycle to the status registe r is in progress will not stop this write operation, but t he operation disables subsequent write attempts to the status register. when wp is high, all functions, including nonvolatile writes to the status register operate no rmally. setting the wpen bit in the status register to 0 blocks the wp pin function, allowing writes to the status register when wp is high or low. setting the wpen bit to 1 while the wp pin is low activates the programmable rom mode, thus requiring a change in the wp pin prior to subsequent status register changes. this allows manufacturing to install the device in a system with wp pin grounded and still be able to p rogram the status register. manufacturing can then load conf iguration data, manufacturing time and other parameters i nto the eeprom, then set the portion of memory to be protect ed by setting the block lock bit s, and finally set the otp mode b y setting the wpen bit. data changes now require a hardware change. read sequence when reading from the eeprom memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the device, follow ed by the 16-bit address. afte r the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically inc remented to the next higher address after each byte of data is shifted out. when the highes t address is reached, the address counter rolls over to address status register bits array addresses protected bl1 bl0 X5323/x5325 0 0 none (factory default) 0 1 $0c00 to $0fff 1 0 $0800 to $0fff 1 1 $0000 to $0fff status register bits watchdog time-out (typical) wd1 wd0 0 0 1.4s 0 1 600ms 1 0 200ms 1 1 disabled (factory default) 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 654321 0 data out cs sck si so msb high impedance instruction 16-bit address 15 14 13 3 2 1 0 figure 5. read eeprom array sequence
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 8 of 19 december 9, 2015 $0000 allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the read eeprom array se quence (figure 1). to read the status register, the cs line is first pulled low to select the device followed by t he 8-bit rdsr instruction. after the rdsr opcode is sent, the c ontents of the status register are shifted out on the so line. refer to the read status regist er sequence (figure 2). write sequence prior to any attempt t o write data into the device, the write enable latch (wel) must firs t be set by issuing the wren instruction (figure 3). cs is first taken lo w, then the wren instruction is clocked into the d evice. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the write o peration without taking cs high after issuing the wren instruc tion, the write operation will be ignored. to write data to the eeprom m emory array, the user then issues the write instruction fo llowed by the 16-bit address and then the data to be written . any unused address bits are specified to be 0s. the writ e operation minimally takes 32 clocks. cs must go low and remain low for the duration of the operation. if the address counte r reaches the end of a page and the clock continues, the co unter will roll back to the firs t address of the page and overwr ite any data that may have been previously written. note: when writing more than one page, you must wait one write cycle (10ms typical) when going from one page to another. this is requir ed for the internal n onvolatile memory t o be programmed correctly. for the page write operation (byte or page write) to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be completed (figure 4 ). to write to the status register, the wrsr instruction is follow ed by the data to be written (figur e 5). data bits 0 and 1 must be 0. while the write is in progress following a status register or eeprom sequence, the status regi ster may be read to check the wip bit. during this t ime the wip bi t will be high. operational notes the device powers-up in the following state: ? the device is in the lo w power standby state. ? a high to low transition on cs is required to enter an active state and receive an instruction. ? so pin is high impedance. ? the write enable latch is reset. ? the flag bit is reset. ? reset signal is active for t purst . data protection the following circuitry has been included to prevent inadvertent writes: ? a wren instruction must be issued to set the write enable latch. ?cs must come high at the pr oper clock count in order to start a nonvolatile write cycle. 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction figure 6. read status register sequence
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 9 of 19 december 9, 2015 symbol table 01234567 cs si sck high impedance so figure 7. write enable latch sequence waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16-bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte n 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 654 321 0 figure 8. write sequence 0123456789 cs sck si so high impedance instruction data byte 765432 10 10 11 12 13 14 15 figure 9. status register write sequence
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 10 of 19 december 9, 2015 absolute maximum ratings thermal information temperature under bias . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on any pin with respect to v ss . . . . . . . . . . . . -1.0v to +7v dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma operating conditions temperature range (industrial) . . . . . . . . . . . . . . . . . -40c to +85c temperature range (commercial). . . . . . . . . . . . . . . . 0 c to +70c supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. dc electrical specifications over the recommended operating cond itions, unless otherwise spe cified parameter symbol test conditions min typ max unit v cc write current (active) i cc1 sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open 5 ma v cc read current (active) i cc2 sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open 0.4 ma v cc standby current wdt = off i sb1 cs = v cc , v in = v ss or v cc , v cc =5.5v 1 a v cc standby current wdt = on i sb2 cs = v cc , v in = v ss or v cc , v cc = 5.5v 50 a v cc standby current wdt = on i sb3 cs = v cc , v in = v ss or v cc , v cc =3.6v 20 a input leakage current i li v in = v ss to v cc 0.110a output leakage current i lo v out = v ss to v cc 0.1 10 a input low voltage v il (note 1) -0.5 v cc x 0.3 v input high voltage v ih (note 1) v cc x 0.7 v cc + 0.5 v output low voltage v ol1 v cc > 3.3v, i ol = 2.1ma 0.4 v output low voltage v ol2 2v < v cc ? 3.3v, i ol = 1ma 0.4 v output low voltage v ol3 v cc ? 2v, i ol = 0.5ma 0.4 v output high voltage v oh1 v cc > 3.3v, i oh = -1.0ma v cc - 0.8 v output high voltage v oh2 2v < v cc ? 3.3v, i oh = -0.4ma v cc - 0.4 v output high voltage v oh3 v cc ?? 2v, i oh = -0.25ma v cc - 0.2 v reset output low voltage v ols i ol = 1ma 0.4 v capacitance t a = +25c, f = 1mhz, v cc = 5v symbol test conditions max unit c out (note 2) output capacitance (so, reset /reset) v out = 0v 8 pf c in (note 2) input capacitance (sck, si, cs , wp )v in = 0v 6 pf notes: 1. v il min and v ih max are for reference only and are not tested. 2. this parameter is periodically sampled and not 100% tested.
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 11 of 19 december 9, 2015 equivalent ac load circuit at 5v v cc serial input timing 5v output 100pf 5v 4.6k ? reset/reset 30pf 2.06k ? 3.03k ? ac test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 ac electrical specifications input pulse levels = v cc x 0.1 to v cc x 0.9; input rise and fall time s = 10ns; input and ouput timin g level = v cc x 0.5. over recommended operating conditions, unless otherwise specified. parameter symbol 2.7 to 5.5v unit min max serial input timing clock frequency f sck 02mhz cycle time t cyc 500 ns cs lead time t lead 250 ns cs lag time t lag 250 ns clock high time t wh 200 ns clock low time t wl 250 ns data set-up time t su 50 ns data hold time t h 50 ns input rise time t ri (note 3) 100 ns input fall time t fi (note 3) 100 ns cs deselect time t cs 500 ns write cycle time t wc (note 4) 10 ms sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 12 of 19 december 9, 2015 serial output timing power-up and power-down timing serial output timing parameter symbol 2.7 to 5.5v unit min max clock frequency f sck 02mhz output disable time t dis 250 ns output valid from clock low t v 250 ns output hold time t ho 0ns output rise time t ro (note 3) 100 ns output fall time t fo (note 3) 100 ns notes: 3. this parameter is periodically sampled and not 100% tested. 4. t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the s elf-timed internal nonvolatile write cycle. sck cs so si msb out msbC1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag reset (X5323) reset (X5323) v cc t purst t purst t r t f t rpd 0v v trip v trip
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 13 of 19 december 9, 2015 cs /wdi vs reset/reset timing reset output timing symbol parameter min typ max unit v trip reset trip point voltage, X5323-4.5a, X5323-4.5a 4.5 4.63 4.75 v reset trip point voltage, X5323, x5325 4.25 4.38 4.5 v reset trip point voltage, X5323-2.7a, x5325-2.7a 2.85 2.92 3.0 v reset trip point voltage, X5323-2.7, x5325-2.7 2.55 2.63 2.7 v v th v trip hysteresis (high to low vs low to high v trip voltage) 20 mv t purst power-up reset time-out 100 200 280 ms t rpd (note 5) v cc detect to reset/output 500 ns t f (note 5) v cc fall time 100 s t r (note 5) v cc rise time 100 s v rvalid reset valid v cc 1v note: 5. this parameter is periodically sampled and not 100% tested. cs /wdi t cst reset t wdo t rst t wdo t rst reset reset /reset output timing symbol parameter min typ max unit t wdo watchdog time-out period wd1 = 1, wd0 = 0 100 200 300 ms wd1 = 0, wd0 = 1 450 600 800 ms wd1 = 0, wd0 = 0 1 1.4 2 s t cst cs pulse width to reset the watchdog 400 ns t rst reset time-out 100 200 300 ms
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 14 of 19 december 9, 2015 v trip set conditions v trip reset conditions sck si v p v p cs t vps t vph t p t vps t vph t rp t vpo t vpo t tsu t thd v trip v cc sck si v cc v p cs t vps t vph t p t vps t vp1 t rp t vpo t vpo v cc * *v cc > programmed v trip v cc = 1.7 to 5.5v; temperature = 0c to +70c. parameter description min max unit t vps sck v trip program voltage set-up time 1 s t vph sck v trip program voltage hold time 1 s t p v trip program pulse width 1s t tsu v trip level set-up time 10 s t thd v trip level hold (stable) time 10 ms
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 15 of 19 december 9, 2015 t wc v trip write cycle time 10 ms t rp v trip program cycle recovery period (between successive programming cycles) 10 ms t vpo sck v trip program voltage off-time before next cycle 0 ms v p programming voltage 15 18 v v tran v trip programed voltage range 1.7 5.0 v v ta1 initial v trip program voltage accuracy (v cc applied-v trip ) (programmed at +25c) -0.1 +0.4 v v ta2 subsequent v trip program voltage accuracy [(v cc applied-v ta1 )-v trip ] (programmed at +25c) -25 +25 mv v tr v trip program voltage repeatability (successive program operations; programmed at +25c) -25 +25 mv v tv v trip program variation after programming (0c to +75c; programmed at +25c) -25 +25 mv note: 6. v trip programming parameters are periodically sampled and are not 10 0% tested. v trip programming specifications v cc = 1.7 to 5.5v; temperature = 0c to +70c. (continued) parameter description min max unit typical performance curves figure 10. v cc supply current vs temperature (i sb ) figure 11. t wdo vs voltage/temperature (wd1, 0 = 1, 1) figure 12. v trip vs temperature (programmed at +25c) figure 13. t wdo vs voltage/temperature (wd1, 0 = 1, 0) 18 16 14 12 10 8 6 4 2 0 -40 25 90 temperature (c) isb (a) watchdog timer off (v cc = 3v, 5v) watchdog timer off (v cc = 3v, 5v) watchdog timer on (v cc = 5v) watchdog timer on (v cc = 5v) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 1.7 2.4 3.1 3.8 4.5 5.2 +90c +25c -40c reset (s) voltage (v) 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 025 85 voltage (v) temperature (c) v trip = 5v v trip = 3.5v v trip = 2.5v 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 1.7 5.2 reset (s) voltage (v) 2.4 3.1 3.8 4.5 +90c +25c -40c
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 16 of 19 december 9, 2015 about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support figure 14. t purst vs temperature figure 15. t wdo vs voltage/temperature (wd1, 0 0 = 0, 1) typical performance curves 200 195 190 185 180 175 170 165 160 -40 25 90 temperature (c) 205 time (ms) +90c +25c -40c 200 195 190 185 180 175 170 165 160 205 reset (s) voltage (v) 1.7 5.2 2.4 3.1 3.8 4.5 the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change december 9, 2015 fn8131.3 updated ordering information table on page 2. added revision history and about intersil sections. replaced pod mdp0027 with m8.15e
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 17 of 19 december 9, 2015 plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol inches tolerance notes pdip8 pdip14 pdip16 pdip18 pdip20 a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. c 2/07 notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the leads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
X5323, x5325 (replaces x25323, x25325) fn8131 rev 3.00 page 18 of 19 december 9, 2015 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise s pecified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side . dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view a typical recomme nded land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view b
fn8131 rev 3.00 page 19 of 19 december 9, 2015 X5323, x5325 (replaces x25323, x25325) intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2003-2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. thin shrink small outlin e plastic packages (tssop) ? index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 ? 0 o 8 o 0 o 8 o - rev. 2 4/06

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